The characteristics of an electronic device are typically defined in terms of a set of data including s-parameters, noise figures, gain tables etc. For packaged RF devices, in addition to the above parameters, the mechanical dimensions of the leads also contribute to electrical performance of the device.
The degree of influence of the device leads on the electrical performance of the device is dependent on the applicable frequency range of operation of the device, the physical dimensions of the device leads and the substrate on which the device is mounted.
For RF applications up to several tens of Gigahertz, the physical dimensions of the device leads can be of critical importance, because at higher frequencies, the device leads have an electrical length which is significant compared to one half of the wavelength for the frequency of operation of the device. Similarly, the type of substrate on which the device is mounted affects the performance of the device, because the electrical characteristics of metalised tracks fabricated on the substrate are determined by the dielectric constant of the substrate material and by the thickness of the substrate.
For such high frequency operation, electrical connections from the device to the input/output terminals of the substrate, or from one device to another on the substrate are usually designed to have the properties of an electrical transmission line with a given characteristic impedance; for example, microstrip, co-planar waveguide, or stripline structures are often employed. Microstrip lines are the industry preferred method of high frequency connection, due to the inherent high loss associated with stripline structures, and due to the need for perfect symmetry in the fabrication of co-planar waveguides.
FIG. 1 shows the physical dimensions of a proprietary packaged field effect transistor (FET) designed for RF applications up to 30 GHz. It can be seen that in the case shown the leads connecting to the gate and to the drain of the FET have a length of 1.5 mm and a width of 0.5 mm. At 30 GHz, a half-wave microstrip line fabricated on a PCB with a dielectric constant of 3.5 has a length of 2.68 mm, so it is apparent that the leads will have a significant effect on the RF performance of the FET of FIG. 1
One approach to minimize the effects of the leads on the RF performance of the FET of FIG. 1 is to mount the FET on a substrate where the electrical connections to the FET are in the form of microstrip transmission lines of specified characteristic impedances, and where the width of each microstrip transmission line is greater than or equal to the width of the corresponding lead on the packaged FET. This method for mounting the FET of FIG. 1 is shown in FIG. 2(a) (top view) and FIG. 2(b) (side view). It can be seen that the device leads have become part of the microstrip transmission lines which connect directly to the gate G and to the drain D of the FET. Also, it can be seen from FIG. 2 that the section of line from the point A to the point B defined by the lead connecting to the gate G of the FET connects seamlessly with the microstrip transmission line at the point A.
The method of RF connection depicted in FIG. 2 eliminates any discontinuities resulting from changes in the widths of the transmission lines at the ends of the FET leads; however, this method of mounting a high frequency FET on a substrate suffers from the drawback that the design of a microstrip line with the preferred characteristic impedance may not be possible when the minimum width of the microstrip line is limited by the width of the FET leads, as shown in FIG. 2.
Consider the substrate on which the FET will be mounted. Typical properties of two common substrate materials, low temperature co-fired ceramic (LTCC) and Teflon fiberglass (often referred to by its proprietary name, Duroid) are given in table 1 below.
TABLE 1Dielectric constant of LTCC and Teflon fiberglassMaterialDielectric Constant εrLTCC7.9Teflon fiberglass2.2
For control of the characteristic impedance of a microstrip line, where the width of the line is restricted to a particular minimum as described above, the thickness of the substrate must be set to a particular value; however, in practice the designer does not have control over the substrate thickness because the range of thickness of commercially available substrates is limited—for example Teflon fiberglass is typically available in integer multiples of 0.254 mm, and because other design factors may dictate the thickness of the substrate to be used.
The two following substrates are used as examples to highlight the problems with obtaining the correct characteristic impedance using microstrip lines for RF connections to the FET as shown in FIG. 2: an LTCC substrate with a thickness of 0.32 mm; and a Teflon fiberglass substrate with a thickness of 0.508 mm. Table 2 gives the resulting characteristic impedance for a microstrip line fabricated on each of the above substrates and for the case where the width of each microstrip line is 0.6 mm (i.e. 0.1 mm greater than the widths of the leads of the FET of FIG. 1). Table 2 also gives the phase delay at 24 GHz for each microstrip line, and for a line length of 1.5 mm (i.e. the same as the lengths of leads of the FET of FIG. 1).
TABLE 2Electrical characteristics of 0.6 mm × 1.5 mm lineson two different substrates.CharacteristicPhase delaySubstrateimpedanceat 24 GHzLTCC, h = 0.32 mm, εr = 7.939 Ω106°Teflon fiberglass, h = 0.508 mm, εr = 2.288 Ω 58°
Thus, it can be seen that a suitably sized microstrip line fabricated on the LTCC substrate of table 2 will have a characteristic impedance of 39 Ohms and will have phase delay of 106°, and that a suitably sized microstrip line fabricated on the Teflon fiberglass substrate of table 2 will have a characteristic impedance of 88 Ohms and will have a phase delay of 58°. In each of the above cases the characteristic impedance of the line can be reduced by increasing the width of the line, but the characteristic impedance cannot be increased, because the minimum width of the line is determined by the dimensions of the FET leads.
For typical RF applications of an FET, matching circuits for the gate and the drain of the FET are provided on the substrate on which the FET is mounted, and each matching circuit is connected either directly to the terminals of the FET or to the terminals of the FET via a microstrip transmission line. The matching circuit or the combination of the matching circuit and the microstrip transmission line provides the optimum terminating impedance at each input of the FET. For example, a particular application of the FET of FIG. 1 requires that the matching circuit be connected to the gate of the FET via a microstrip line with a characteristic impedance of 120 Ohms.
FIG. 3 shows a high impedance microstrip line connecting from a remotely located matching circuit to the gate G of the FET. It can be seen that the high impedance microstrip transmission line which connects from the remotely located matching circuit to the gate G of the FET, is inevitably connected to the FET via the low impedance line defined by the lead of the FET which extends from point A to point B of FIG. 3.
As described above, the low impedance transmission line extending from point A to point B in FIG. 3 will have a characteristic impedance of 39 Ohms for the LTCC substrate of table 2 and 88 Ohms for the Teflon fibreglass substrate of table 2. Moreover, since the phase delay of each microstrip line given in table 2 is respectively 106° and 58°, the impedance presented at the input of the FET B, will be substantially different from the optimum value at the end of the high impedance microstrip transmission line, at the point A on the substrate.
An alternative to the method of mounting a high frequency FET on a substrate to that depicted in FIG. 2 and FIG. 3, is to employ a multilayer substrate as illustrated in FIG. 4(a) (top view) and FIG. 4(b) (side view). The multilayer substrate of FIG. 4 comprises solder pads for the FET on the top surface of the substrate and further comprises microstrip connecting lines which are embedded on a sub-layer of the multilayer substrate. Electrical connections from the embedded microstrip lines to the solder pads on the top surface of the substrate are made by electrically conducting via holes which run from the microstrip lines on the sub layer to the top surface.
The method of mounting a high frequency FET on a substrate depicted in FIG. 4 is often preferred for mass production purposes, because the FET will self-align during re-flow soldering if the top surface comprises only RF pads for the device. This method is also preferred in cases where a number of devices share the same substrate, and where the tracks connecting each device would inevitably cross over if they were fabricated on the top layer of the substrate. However the track ends and via holes which result from adopting this approach introduce discontinuities in the microstrip lines which degrade the matching of the microstrip lines to the terminating impedances at each end. Furthermore, the method of mounting a high frequency FET on a substrate depicted in FIG. 4 does not solve the problems which arise from the physical dimensions of the leads of the FET as described earlier.